1. Field of the Invention
The present invention relates generally to an apparatus and method for controlling power supply and power distribution system noise. More specifically, the present invention provides a method and apparatus for mitigating power supply and power distribution system noise response by throttling execution units based upon voltage sensing.
2. Description of the Related Art
Power supply and power distribution system noise, especially dips due to large step activity increases in a microprocessor are a limiting factor in how fast the circuits in such a processor can operate. This limits either the system operating frequency or limits chips that can yield at any given objective frequency. Traditionally, decoupling capacitors have been used to limit the magnitude of this noise. However, as design frequencies have risen over the years, decoupling capacitance is becoming either less effective at the frequencies that are required to have an effect, or are too costly in financial terms or power dissipation terms. That is, in terms of chip real estate and oxide leakage impact on chip power requirements.
Electrical distance from capacitor placement sites to circuits on chips constrained by physical space availability can make discrete capacitors completely or nearly ineffective. Prior art has discussed throttling of code execution scheduling when transitions from low to high activity are requested. However, the performance impact of stalling executions during every transition from a low activity state to a high activity state has a significant cost impact on performance. FIG. 1 is a chart depicting an example plot, designated as 102, of the voltage droop that can occur with a transition of execution demand of nearly 0% capacity to 90% of capacity. Droop is the difference between the set point and the actual operating or control point. The left axis represents the voltage, from −0.1 to 0.04, where 0=Vdc at the minimum load. Vdc is the DC voltage. Therefore, the statement 0=Vdc at the minimum load means that background DC voltage at the minimum load has been removed from the chart and all that is left is the noise. The right axis represents the number of stalled executions, from 0 to 200. The horizontal axis represents the number of nanoseconds (ns) that have passed, ranging from 0 to 800 ns.
The 90 mv (millivolt) plus droop from the no load voltage, shown in 102, determines the limits of the maximum operating capability of the processor even though it occurs only sporadically.